A semiconductor memory may have redundancy when replacing a defective memory cell with a redundant memory cell. When a defective memory cell is discovered due to an operational test performed on memory cells before shipping the semiconductor memory, the location information of the defective memory cell is stored in, for example, a fuse circuit. Based on the location information of the defective memory cell, a redundant memory cell is accessed in a read operation instead of the defective memory cell. The defective memory cell may be replaced with the redundant memory cell in units of data bits, word lines, or column lines.
The fuse circuit may include a latch circuit that corresponds to one fuse and latches data for indicating a state of the fuse, that is, whether or not the fuse is cut off. For example, when the defective memory cell is repaired in units of data bits, a redundant memory block is prepared and a memory block including a defective data bit is replaced with the redundant memory block. The location of the defective data bit is stored in the fuse circuit to replace the memory block including the defective data bit with the redundant memory block.
When the number of data bits is 32 for example, six fuse circuits may be provided. The locations of the 32 data bits may be designated with five fuse circuits. However, since it is desirable to further designate use or nonuse of the redundancy, a total of six fuse circuits may be needed. Each group of the six fuse circuits is referred to as a fuse group. Based on a code indicating the location of a defective data bit, at least one of the fuses in the fuse group is cut off. Information regarding the fuse that has been cut off is supplied to a redundant switch circuit through a corresponding latch circuit. Based on the information regarding the fuse that has been cut off, the redundant switch circuit replaces a memory block corresponding to the location of the defective data bit with a redundant memory block.
When a semiconductor chip is handled, such as a system on chip (SoC), a memory built-in self test (MBIST) circuit is provided around each memory. The MBIST circuit is used, for example, to generate a test pattern and determine a memory test result. A self repair operation called “built-in self repair (BISR)” for automatically replacing a defective portion with a redundant memory cell may be performed in the chip when the defective portion is found in the memory by a self check operation, such as a built-in self test (BIST). The defective portion may be repaired with the BISR without outputting the memory test result (information regarding the memory cell corresponding to the defective portion) to a large scale integration (LSI) tester outside the chip. Accordingly, the memory may be repaired efficiently at a high speed.
Preferably, two or more redundant memory cells and fuse groups are prepared to repair two or more defective portions individually so that the yield rate of the memory may increase. When the redundant operation is performed in units of data bits for example, up to two defective data bits may be repaired with two redundant memory blocks and two fuse groups. When two or more fuse groups are used in a configuration for the BISR as described above, the allocation of the fuse groups to one or more found defective portions is determined.
Since some memory cells are found defective in a test performed under certain voltage and temperature conditions, the memory test is desirably performed two or more times under different voltage and temperature conditions. When the memory test is performed two or more times, a defective portion is repaired each time one test operation is finished. That is, another fuse group is allocated as a target to be cut off instead of a fuse group that has already been cut off in a previous test, each time a defective portion is discovered in a new memory test operation.